? semiconductor components industries, llc, 2006 june, 2006 ? rev. 12 1 publication order number: mc100lvep210/d mc100lvep210 2.5v / 3.3v1:5 dual differential ecl/pecl/hstl clock driver description the mc100lvep210 is a low skew 1 ? to ? 5 dual dif ferential driver, designed with clock distribution in mind. the ecl/pecl input signals can be either differential or single ? ended if the v bb output is used. the signal is fanned out to 5 identical dif ferential outputs. hstl inputs can be used when the ep210 is operating in pecl mode. the lvep210 specifically guarantees low output ? to ? output skew. optimal design, layout, and processing minimize skew within a device and from device to device. to ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 even if only one output is being used. if an output pair is unused, both outputs may be left open (unterminated) without affecting skew. the mc100lvep210, as with most other ecl devices, can be operated from a positive v cc supply in pecl mode. this allows the lvep210 to be used for high performance clock distribution in +3.3 v or +2.5 v systems. single ? ended clk input operation is limited to a v cc 3.0 v in pecl mode, or v ee ? 3.0 v in ecl mode. designers can take advantage of the lvep210?s performance to distribute low skew clocks across the backplane or the board. in a pecl environment, series or thevenin line terminations are typically used as they require no additional power supplies. for more information on using pecl, designers should refer to application note an1406/d. features ? 85 ps typical device ? to ? device skew ? 20 ps typical output ? to ? output skew ? v bb output ? jitter less than 1 ps rms ? 350 ps typical propagation delay ? maximum frequency 3 ghz typical ? the 100 series contains temperature compensation ? pecl and hstl mode operating range: v cc = 2.375 v to 3.8 v with v ee = 0 v ? necl mode operating range: v cc = 0 v with v ee = ? 2.375 v to ? 3.8 v ? open input default state ? lvds input compatible ? fully compatible with mc100ep210 ? pb ? free packages are available* *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. 32 ? lead lqfp fa suffix case 873a marking diagram* a = assembly location wl = wafer lot yy = year ww = work week g= pb ? free package http://onsemi.com *for additional marking information, refer to application note and8002/d. see detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. ordering information mc100 lvep21 awlyywwg
mc100lvep210 http://onsemi.com 2 clkn*, clkn ** ecl/pecl/hstl clk inputs v bb reference voltage output v cc 25 26 27 28 29 30 31 32 15 14 13 12 11 10 9 12345678 24 23 22 21 20 19 18 17 16 qb4 qb4 qb3 qb3 qb2 qb2 v cc v cc qa0 qa0 qa1 qa1 qa2 qa2 v cc v ee v bb v cc qb1 qb1 qb0 qb0 qa4 qa4 qa3 qa3 qa0 qa0 qa1 qa1 qa2 qa2 qa3 qa3 qa4 qa4 v bb clka clka nc qb0 qb0 qb1 qb1 qb2 qb2 qb3 qb3 qb4 qb4 clkb clkb warning: all v cc and v ee pins must be externally connected to power supply to guarantee proper operation. pin qn0:4, qn0:4 ecl/pecl outputs function v cc positive supply v ee negative supply figure 1. lqfp ? 32 pinout (top view) figure 2. logic diagram * pins will default low when left open. ** pins will default to v cc /2 when left open. mc100lvep210 clka clka clkb clkb v ee v cc table 1. pin description table 2. attributes characteristics value internal input pulldown resistor 75 k internal input pull ? up resistor 37.5 k esd protection human body model machine model charged device model > 2 kv > 100 v > 2 kv moisture sensitivity (note 1) level 2 flammability rating oxygen index: 28 to 34 ul 94 v ? 0 @ 0.125 in transistor count 461 devices meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, see application note and8003/d.
mc100lvep210 http://onsemi.com 3 table 3. maximum ratings symbol parameter condition 1 condition 2 rating unit v cc pecl mode power supply v ee = 0 v 6 v v ee necl mode power supply v cc = 0 v ? 6 v v i pecl mode input voltage necl mode input voltage v ee = 0 v v cc = 0 v v i v cc v i v ee 6 ? 6 v v i out output current continuous surge 50 100 ma ma i bb v bb sink/source 0.5 ma t a operating temperature range ? 40 to +85 c t stg storage temperature range ? 65 to +150 c q ja thermal resistance (junction ? to ? ambient) 0 lfpm 500 lfpm lqfp ? 32 lqfp ? 32 80 55 c/w c/w jc thermal resistance (junction ? to ? case) standard board lqfp ? 32 12 to 17 c/w t sol wave solder pb pb ? free <2 to 3 sec @ 248 c <2 to 3 sec @ 260 c 265 265 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. table 4. pecl dc characteristics v cc = 2.5 v; v ee = 0 v (note 2) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 70 90 55 70 90 55 70 90 ma v oh output high voltage (note 3) 1355 1480 1605 1355 1480 1605 1355 1480 1605 mv v ol output low voltage (note 3) 555 680 900 555 680 900 555 680 900 mv v ihcmr input high voltage common mode range (differential configuration) (note 4) 1.2 2.5 1.2 2.5 1.2 2.5 v v il input low voltage (single ? ended) 555 900 555 900 555 900 mv i ih input high current 150 150 150 a i il input low current clk clk 0.5 ? 150 0.5 ? 150 0.5 ? 150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. input and output parameters vary 1:1 with v cc . v ee can vary + 0.125 v to ? 1.3 v. 3. all loading with 50 to v ee . 4. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc100lvep210 http://onsemi.com 4 table 5. pecl dc characteristics v cc = 3.3 v; v ee = 0 v (note 5) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 70 90 55 70 90 55 70 90 ma v oh output high voltage (note 6) 2155 2280 2405 2155 2280 2405 2155 2280 2405 mv v ol output low voltage (note 6) 1355 1480 1700 1355 1480 1700 1355 1480 1700 mv v ih input high voltage (single ? ended) 2135 2420 2135 2420 2135 2420 mv v il input low voltage (single ? ended) 1355 1700 1355 1700 1355 1700 mv v bb output reference voltage (note 7) 1775 1875 1975 1775 1875 1975 1775 1875 1975 mv v ihcmr input high voltage common mode range (differential configuration) (note 8) 1.2 3.3 1.2 3.3 1.2 3.3 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 ? 150 0.5 ? 150 0.5 ? 150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 5. input and output parameters vary 1:1 with v cc . v ee can vary + 0.925 v to ? 0.5 v. 6. all loading with 50 to v cc ? 2.0 v. 7. single ? ended input operation is limited v cc 3.0 v in pecl mode. 8. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. table 6. necl dc characteristics v cc = 0 v, v ee = ? 2.375 v to ? 3.8 v (note 9) ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 55 70 90 55 70 90 55 70 90 ma v oh output high voltage (note 10) ? 1145 ? 1020 ? 895 ? 1145 ? 1020 ? 895 ? 1145 ? 1020 ? 895 mv v ol output low voltage (note 10) ? 1945 ? 1820 ? 1600 ? 1945 ? 1820 ? 1600 ? 1945 ? 1820 ? 1600 mv v ih input high voltage (single ? ended) ? 1165 ? 880 ? 1165 ? 880 ? 1165 ? 880 mv v il input low voltage (single ? ended) ? 1945 ? 1600 ? 1945 ? 1600 ? 1945 ? 1600 mv v bb output reference voltage (note 11) ? 1525 ? 1425 ? 1325 ? 1525 ? 1425 ? 1325 ? 1525 ? 1425 ? 1325 mv v ihcmr input high voltage common mode range (differential configuration) (note 12) v ee + 1.2 0.0 v ee + 1.2 0.0 v ee + 1.2 0.0 v i ih input high current 150 150 150 a i il input low current clk clk 0.5 ? 150 0.5 ? 150 0.5 ? 150 150 a note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 9. input and output parameters vary 1:1 with v cc . 10. all loading with 50 to v cc ? 2.0 v. 11. single ? ended input operation is limited v ee ? 3.0v in necl mode. 12. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal.
mc100lvep210 http://onsemi.com 5 table 7. hstl dc characteristics v cc = 2.375 to 3.8 v, v ee = 0 v ? 40 c 25 c 85 c symbol characteristic min typ max min typ max min typ max unit v ih input high voltage 1200 1200 1200 mv v il input low voltage 400 400 400 mv v cm input crossover voltage 680 900 680 900 680 900 mv i cc power supply current (outputs open) 55 70 90 55 70 90 55 70 90 ma note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. table 8. ac characteristics v cc = 0 v; v ee = ? 2.375 to ? 3.8 v or v cc = 2.375 to 3.8 v; v ee = 0 v (note 13) symbol characteristic ? 40 c 25 c 85 c unit min typ max min typ max min typ max f maxpecl/ hstl maximum frequency (figure 3) 3 3 3 ghz t plh t phl propagation delay propagation delay @ 2.5 v 220 300 380 270 350 430 300 330 500 410 750 490 ps t skew within ? device skew (note 14) device ? to ? device skew (note 15) 20 85 25 160 20 85 25 160 20 85 35 160 ps t jitter clock random jitter (rms) @ 0.5 ghz @ 1.0 ghz @ 1.5 ghz @ 2.0 ghz @ 2.5 ghz @ 3.0 ghz 0.184 0.190 0.178 0.196 0.239 0.336 0.3 0.3 0.3 0.3 0.4 0.5 0.207 0.200 0.197 0.233 0.301 0.422 0.3 0.3 0.3 0.4 0.4 0.5 0.271 0.252 0.259 0.308 0.399 0.572 0.4 0.4 0.4 0.5 0.5 0.9 ps v pp minimum input swing 150 800 1200 150 800 1200 150 800 1200 mv t r /t f output rise/fall time (20% ? 80%) 100 170 250 120 190 270 150 280 350 ps note: device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printe d circuit board with maintained transverse airflow greater than 500 lfpm. electrical parameters are guaranteed only over the declared operating temperature range. functional operation of the device exceeding these conditions is not implied. device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 13. measured with 750 mv source, 50% duty cycle clock source. all loading with 50 to v cc ? 2.0 v. 14. skew is measured between outputs under identical transitions of similar paths through a device. 15. device ? to ? device skew for identical transitions at identical v cc levels.
mc100lvep210 http://onsemi.com 6 0 100 200 300 400 500 600 700 800 0 1000 2000 3000 4000 5000 6000 figure 3. f max typical frequency (mhz) v outpp (mv) figure 4. typical termination for output driver and device evaluation (see application note and8020/d ? termination of ecl logic devices.) driver device receiver device qd q d z o = 50 z o = 50 50 50 v tt v tt = v cc ? 2.0 v ordering information device package shipping ? mc100lvep210fa lqfp 250 units/tray MC100LVEP210FAG lqfp (pb ? free) 250 units/tray mc100lvep210far2 lqfp 2000 tape & reel mc100lvep210farg lqfp (pb ? free) 2000 tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
mc100lvep210 http://onsemi.com 7 resource reference of application notes an1405/d ? ecl clock distribution techniques an1406/d ? designing with pecl (ecl at +5.0 v) an1503/d ? eclinps i/o spice modeling kit an1504/d ? metastability and the eclinps family an1568/d ? interfacing between lvds and ecl an1642/d ? the ecl translator guide and8001/d ? odd number counters design and8002/d ? marking and date codes and8020/d ? termination of ecl logic devices and8066/d ? interfacing with eclinps and8090/d ? ac characteristics of ecl devices
mc100lvep210 http://onsemi.com 8 package dimensions 1 8 9 17 25 32 ae ae p detail y base n j d f metal section ae ? ae g seating plane r q w k x 0.250 (0.010) gauge plane e c h detail ad detail ad a1 b1 v1 4x s 4x 9 ? t ? ? z ? ? u ? t?u 0.20 (0.008) z ac t?u 0.20 (0.008) z ab 0.10 (0.004) ac ? ac ? ? ab ? m 8x ? t ? , ? u ? , ? z ? t?u m 0.20 (0.008) z ac 32 lead lqfp case 873a ? 02 issue c notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane ? ab ? is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ? t ? , ? u ? , and ? z ? to be determined at datum plane ? ab ? . 5. dimensions s and v to be determined at seating plane ? ac ? . 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.250 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane ? ab ? . 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.520 (0.020). 8. minimum solder plate thickness shall be 0.0076 (0.0003). 9. exact shape of each corner may vary from depiction. dim a min max min max inches 7.000 bsc 0.276 bsc millimeters b 7.000 bsc 0.276 bsc c 1.400 1.600 0.055 0.063 d 0.300 0.450 0.012 0.018 e 1.350 1.450 0.053 0.057 f 0.300 0.400 0.012 0.016 g 0.800 bsc 0.031 bsc h 0.050 0.150 0.002 0.006 j 0.090 0.200 0.004 0.008 k 0.450 0.750 0.018 0.030 m 12 ref 12 ref n 0.090 0.160 0.004 0.006 p 0.400 bsc 0.016 bsc q 1 5 1 5 r 0.150 0.250 0.006 0.010 v 9.000 bsc 0.354 bsc v1 4.500 bsc 0.177 bsc b1 3.500 bsc 0.138 bsc a1 3.500 bsc 0.138 bsc s 9.000 bsc 0.354 bsc s1 4.500 bsc 0.177 bsc w 0.200 ref 0.008 ref x 1.000 ref 0.039 ref
mc100lvep210 http://onsemi.com 9 on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 mc100lvep210/d eclinps is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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